10. CACHE Instructions

10.5 Index Load Tag (I)

Index Load Tag (I) reads the primary instruction cache tag fields into the CP0 TagLo and TagHi registers. VA[13:6] defines the address and VA[0] defines the way of the tag to be read.

All parity errors caused by Index Load Tag (I) are ignored.

The following mapping defines the operation:

TagLo[0] = Tag parity bit

TagLo[2] = State parity bit

TagLo[3] = LRU bit

TagLo[6] = State bit

TagLo[31:8] = Tag[35:12]

TagHi[3:0] = Tag[39:36]

All other CP0 TagLo and TagHi bits are set to 0.

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